IEEE

Spread-spectrum clock generator for serial ATA using fractional PLL controlled by /spl Delta//spl Sigma/ modulator with level shifter

Abstract: Implemented in a 0.15/spl mu/m CMOS process, the spread-spectrum clock generator uses the fractional PLL controlled by a /spl Delta//spl Sigma/ modulator An adaptive level shifter is adopted ...
IEEE

A 32nm, 0.65–10GHz, 0.9/0.3 ps/σ TX/RX jitter single inductor digital fractional-n clock generator for reconfigurable serial I/O

Abstract: In CPU, SOC, GPU, and PC-on-chip, I/O power consumption can be significant. To improve power efficiency, I/O bundles in group of 4, 8, or 16b, should scale their data rate according to the ...