Design-Reuse

IP Cores, Inc. Announces Two New Multi-Gigabit IP Combo AES/LRW and AES/GCM Cores for System on Chip (SoC) Design

Starting at 30K ASIC gates and delivering up to 10 Gbps throughput, GLM1 and GLM2 cores provide a compact and efficient solution for an SoC designer working on a secure IEEE P1619 storage or IEEE ...
EDN

FPGA IP cores enable flexible SoC design

This product is featured in EDN's Hot 100 products of 2015. See all 100 here. Optimized for TSMC’s 28-nm process, Menta’s predefined off-the-shelf IP cores for complex SoC devices simplify ...
Design-Reuse

Xilinx Accelerates System Verification with Vivado Design Suite 2015.1

SAN JOSE, Calif. -- May 4, 2015 -- Xilinx, Inc. (NASDAQ: XLNX) today announced acceleration of system verification with the release of the Vivado® Design Suite 2015.1, featuring major productivity ...
Semiconductor Engineering

Why SoC Designers Need Purpose-Built Semiconductor IP Catalog Tools

Semiconductor intellectual property (IP) management, reuse, and change tracking are essential for efficiently creating chip designs based on proven building blocks, reducing your time-to-market, and ...