TechRepublic

Low Power VLSI CMOS Design by DCG Technique

The demand for power-sensitive design has grown significantly in recent years due to tremendous growth in portable applications. Consequently, the need for power efficient design techniques has grown ...
Electronics Weekly

VLSI Symposium: 7bit 150Gsample/s DAC on 5nm CMOS

Imec built a 7bit 150Gsample/s digital to analogue converter using 5nm finfet CMOS. Revealed at the Symposium on VLSI Technology and Circuits in Kyoto, it achieves data rates of up to 300 Gbit/s using ...
EDN

Power dissipation in portables: Design considerations using low-power CMOS ICs

When a CMOS circuit is in an idle state there is still some static power dissipation–a result of leakage current through nominally off transistors. Both nMOS and pMOS transistors used in CMOS logic ...
Electronics Weekly

VLSI Symposium: Imec’s low-power UWB transceiver ranges to 1.4mm

Belgian lab Imec is claiming record ranging precision and power consumption for a novel 6 – 9GHz IEEE 802.15.4z UWB (ultra-wide-band) impulse-radio transceiver: 1.4mm ranging, and 8.7mW Tx plus 21mW ...
Electronic Design

Simplifying VLSI System Power Design

Today’s complex VLSI devices also have complex power requirements, often using several different supply voltages for the core, peripheral, and I/O logic, some of which need to vary depending on ...